View PCF8534AHL1_4642810.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PCF8534A
Universal LCD driver for low multiplex rates
Rev. 05 -- 6 August 2009 Product data sheet
1. General description
The PCF8534A is a peripheral device which interfaces to almost any LCD1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 60 segments. In addition, the PCF8534A can be easily cascaded for larger LCD applications. The PCF8534A is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized using display RAM with auto-incremented addressing, hardware subaddressing and display memory switching (static and duplex drive modes). The PCF8534AH only complies with the AEC-Q100 automotive qualification standard.
2. Features
I Single-chip LCD controller and driver I Selectable backplane drive configurations: static or 2, 3 or 4 backplane multiplexing I 60 segment outputs allowing to drive: N 30 7-segment numeric characters N 16 14-segment alphanumeric characters N Any graphics of up to 240 elements I Cascading supported for larger applications I 60 x 4-bit display data storage RAM I Wide LCD supply range: from 2.5 V for low threshold LCDs up to 6.5 V for guest-host LCDs and high threshold (automobile) twisted nematic LCDs I Internal LCD bias generation with voltage follower buffers I Selectable display bias configurations: static, 12 or 13 I Wide logic power supply range: from 1.8 V to 5.5 V I LCD and logic supplies may be separated I Low power consumption I 400 kHz I2C-bus interface I Compatible with any microprocessors or microcontrollers I No external components I Display memory bank switching in static and duplex drive modes I Auto-incremented display data loading I Versatile blinking modes I Silicon gate CMOS process
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19.
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1. Ordering information Package Name PCF8534AH/1 PCF8534AHL/1 PCF8534AU/DA/1 LQFP80 LQFP80 PCF8534AU Description plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm wire bond die; 76 bonding pads; 2.91 x 2.62 x 0.38 mm Delivery form tape and reel tape and reel chip in tray Version SOT315-1 SOT315-1 PCF8534AU Type number
4. Marking
Table 2. Marking codes Marking code PCF8534AH PCF8534AHL PC8534A-1 Type number PCF8534AH/1 PCF8534AHL/1 PCF8534AU/DA/1
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
2 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
5. Block diagram
BP0 BP1 BP2 BP3 S0 to S59
60
VLCD
BACKPLANE OUTPUTS
DISPLAY SEGMENT OUTPUTS
LCD VOLTAGE SELECTOR
DISPLAY REGISTER DISPLAY CONTROL OUTPUT BANK SELECT AND BLINK CONTROL
VSS
LCD BIAS GENERATOR
PCF8534A
CLK SYNC CLOCK SELECT AND TIMING BLINKER TIMEBASE
DISPLAY RAM
OSC
OSCILLATOR
POWER-ON RESET
COMMAND DECODE
WRITE DATA CONTROL
DATA POINTER AND AUTO INCREMENT
SCL SDA
INPUT FILTERS
I2C-BUS CONTROLLER
SUBADDRESS COUNTER
SA0
VDD
A0
A1
A2
001aah614
Fig 1.
Block diagram of PCF8534A
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
3 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
80 S30 79 S29 78 S28 77 S27 76 S26 75 S25 74 S24 73 S23 72 S22 71 S21 70 S20 69 S19 68 S18 67 S17 66 S16 65 S15 64 S14 63 S13 62 S12 61 S11
S31 S32 S33 S34 S35 S36 S37 S38 S39
1 2 3 4 5 6 7 8 9
60 S10 59 S9 58 S8 57 S7 56 S6 55 S5 54 S4 53 S3 52 S2 51 S1 50 S0 49 VLCD 48 VSS 47 SA0 46 A2 45 A1 44 A0 43 OSC 42 SYNC 41 VDD S51 21 S52 22 S53 23 S54 24 S55 25 S56 26 S57 27 S58 28 S59 29 BP0 30 BP1 31 BP2 32 BP3 33 n.c. 34 n.c. 35 n.c. 36 n.c. 37 SDA 38 SCL 39 CLK 40
S40 10 S41 11 S42 12 S43 13 S44 14 S45 15 S46 16 S47 17 S48 18 S49 19 S50 20
PCF8534AH
001aag092
Top view. For mechanical details, see Figure 24.
Fig 2.
Pin configuration of PCF8534AH/1 (SOT315-1)
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
4 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
80 S30
79 S29
78 S28
77 S27
76 S26
75 S25
74 S24
73 S23
72 S22
71 S21
70 S20
69 S19
68 S18
67 S17
66 S16
65 S15
64 S14
63 S13
62 S12
S31 S32 S33 S34 S35 S36 S37 S38 S39
1 2 3 4 5 6 7 8 9
61 S11
60 S10 59 S9 58 S8 57 S7 56 S6 55 S5 54 S4 53 S3 52 S2 51 S1 50 S0 49 VLCD 48 VSS 47 SA0 46 A2 45 A1 44 A0 43 OSC 42 SYNC 41 VDD S51 21 S52 22 S53 23 S54 24 S55 25 S56 26 S57 27 S58 28 S59 29 BP0 30 BP1 31 BP2 32 BP3 33 n.c. 34 n.c. 35 n.c. 36 n.c. 37 SDA 38 SCL 39 CLK 40
S40 10 S41 11 S42 12 S43 13 S44 14 S45 15 S46 16 S47 17 S48 18 S49 19 S50 20
PCF8534AHL
013aaa158
Top view. For mechanical details, see Figure 24.
Fig 3.
Pin configuration of PCF8534AHL/1 (SOT315-1)
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
5 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
S50 S49 S48 S47 S46
S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 58 57 56 55 54 53 52 51 50 49 48 47
63 62 61 60 59
46 45 44
C1 S51 S52 S53 S54 S55 S56 S57 S58 S59 BP0 BP1 BP2 BP3 SDA 64 65 66 67 68 69 70 71 72 73 74 75 76 1
S33 S32 S31
C2 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11
PCF8534A-1
SCL CLK
2 3 10 11 12 VLCD F 13 14 15 16 17 18 19 20 21 22 23 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 4 5 6 7 8 9
VDD
OSC
SYNC
SA0
Top view
VSS
A0
A1
A2
001aai648
For mechanical details, see Figure 25.
Fig 4.
PCF8534AU/DA/1 pin configuration (bare die)
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
6 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
6.2 Pin description
Table 3. Symbol S31 to S59 BP0 to BP3 n.c. SDA SCL CLK VDD SYNC OSC A0 to A2 SA0 VSS VLCD S0 to S30
[1]
Pin description Pin SOT315-1 Bare die 1 to 29 30 to 33 34 to 37 38 39 40 41 42 43 44 to 46 47 48 49 50 to 80 44 to 72 73 to 76 1 2 3 4 5 6 7 to 9 10 11[1] 12 13 to 43 LCD segment output 31 to 59 LCD backplane output 0 to 3 not connected I2C-bus serial data input and output I2C-bus serial clock input external clock input and internal clock output supply voltage cascade synchronization input and output (active LOW) enable input for internal oscillator subaddress counter input 0 to 2 I2C-bus slave address input 0 ground input of LCD supply voltage LCD segment output 0 to 30 Description
The substrate (rear side of the die) is wired to VSS but should not be electrically connected.
7. Functional description
The PCF8534A is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 60 segments. The display configurations possible with the PCF8534A depend on the number of active backplane outputs required. Display configuration selection is shown in Table 4. All of the display configurations can be implemented in the typical system shown in Figure 5.
Table 4. Number of Backplanes 4 3 2 1 Elements 240 180 120 60 Selection of display configurations 7-segment numeric Digits 30 22 15 7 Indicator symbols 30 26 15 11 14-segment numeric Characters 16 12 8 4 Indicator symbols 16 12 8 4 240 (4 x 60) 180 (3 x 60) 120 (2 x 60) 60 (1 x 60) Dot matrix
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
7 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
VDD
R
tr 2Cb
SDA SCL OSC
VDD
VLCD
60 segment drives
LCD PANEL
HOST MICROPROCESSOR/ MICROCONTROLLER
PCF8534A
4 backplanes
(up to 240 elements)
A0 VSS
A1
A2
SA0 VSS
001aah616
Fig 5.
Typical system configuration
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCF8534A. Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The internal oscillator is selected by connecting pin OSC to VSS. The only other connections required to complete the system are the power supplies (pins VDD, VSS and VLCD) and the LCD panel selected for the application.
7.1 Power-on reset
At power-on the PCF8534A resets to a default starting condition:
* * * * * * * *
All backplane outputs are set to VLCD All segment outputs are set to VLCD The selected drive mode is: 1:4 multiplex with 13 bias Blinking is switched off Input and output bank selectors are reset The I2C-bus interface is initialized The data pointer and the subaddress counter are cleared (set to logic 0) The display is disabled
Do not transfer data on the I2C-bus after a power-on for at least 1 ms to allow the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three series resistors connected between pins VLCD and VSS. The center resistor is switched out of the circuit to provide the 12 bias voltage level for the 1:2 multiplex configuration.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command (see Table 10) from the command decoder. The biasing
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
8 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in Table 5.
Table 5. LCD drive mode static 1:2 multiplex 1:2 multiplex 1:3 multiplex 1:4 multiplex Discrimination ratios LCD bias Backplanes Levels configuration 1 2 2 3 4 2 3 4 4 4 static
1 2 1 3 1 3 1 3
Number of:
V off ( RMS ) -------------------------V LCD
0 0.354 0.333 0.333 0.333
V on ( RMS ) V on ( RMS ) ------------------------ D = -------------------------V off ( RMS ) V LCD
1 0.791 0.745 0.638 0.577 2.236 2.236 1.915 1.732
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3 x Vth. Multiplex drive modes of 1:3 and 1:4 with 12 bias are possible but the discrimination and hence the contrast ratios are smaller.
1 Bias is calculated by ------------ , where the values for a are 1+a
a = 1 for 12 bias a = 2 for 13 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1: V on ( RMS ) =
V LCD
1 (n - 1) 1 2 -- + ---------------- x ------------ n n 1 + a
(1)
where the values for n are n = 1 for static mode n = 2 for 1:2 multiplex n = 3 for 1:3 multiplex n = 4 for 1:4 multiplex The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: V off ( RMS ) = a 2 - 2a + n ----------------------------2 n x (1 + a) (2)
V LCD
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
V on ( RMS ) D = ----------------------- = V off ( RMS )
(a + 1) + (n - 1) ------------------------------------------2 (a - 1) + (n - 1)
2
(3)
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
9 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1 1 2 bias 2 bias
is
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
21 is ---------- = 1.528 . 3
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows:
* 1:3 multiplex (12 bias): V LCD = 6 x V off ( RMS ) = 2.449V off ( RMS )
) * 1:4 multiplex (12 bias): V LCD = ( 4 x 3 - = 2.309V off ( RMS ) ---------------------
3
These compare with V LCD = 3V off ( RMS ) when 13 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage.
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
10 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Figure 6.
Tfr VLCD BP0 VSS VLCD Sn VSS VLCD state 1 (on) state 2 (off) LCD segments
Sn+1
VSS (a) Waveforms at driver. VLCD
state 1
0V
-VLCD VLCD
state 2
0V
-VLCD (b) Resultant waveforms at LCD segment.
mgl745
Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = VLCD. Vstate2(t) = V(Sn + 1)(t) - VBP0(t). Voff(RMS) = 0 V.
Fig 6.
Static drive mode waveforms
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
11 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8534A allows the use of 12 bias or 13 bias in this mode as shown in Figure 7 and Figure 8.
Tfr VLCD BP0 VLCD / 2 VSS state 1 VLCD BP1 VLCD / 2 VSS VLCD Sn VSS VLCD state 2 LCD segments
Sn+1
VSS (a) Waveforms at driver. VLCD VLCD / 2 state 1 0V -VLCD / 2 -VLCD VLCD VLCD / 2 state 2 0V -VLCD / 2 -VLCD (b) Resultant waveforms at LCD segment.
mgl746
Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.354VLCD.
Fig 7.
Waveforms for the 1:2 multiplex drive mode with 12 bias
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
12 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD (b) Resultant waveforms at LCD segment.
mgl747
LCD segments
state 1 state 2
Sn+1
Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD.
Fig 8.
Waveforms for the 1:2 multiplex drive mode with 13 bias
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
13 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Figure 9.
Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD Sn+2 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD state 1 state 2 LCD segments
BP1
BP2
(b) Resultant waveforms at LCD segment.
mgl748
Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD.
Fig 9.
Waveforms for the 1:3 multiplex drive mode with 13 bias
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
14 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 10.
Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD state 1 state 2 LCD segments
BP1
BP3
Sn
Sn+1
Sn+2
2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3
Sn+3
state 1
0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3
state 2
0V -VLCD / 3 -2VLCD / 3 -VLCD
(b) Resultant waveforms at LCD segment.
mgl749
Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD.
Fig 10. Waveforms for the 1:4 multiplex drive mode with 13 bias
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
15 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCF8534A are timed by the frequency fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency fclk(ext). The clock frequency fclk determines the LCD frame frequency (ffr).
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the output from pin CLK is the clock signal for any cascaded PCF8534A in the system. After power-on, SDA must be HIGH to guarantee that the clock starts.
7.5.2 External clock
Connecting pin OSC to VDD enables an external clock source. Pin CLK becomes the external clock input. A clock signal must always be applied to the device, removing the clock can freeze the LCD in a DC state.
7.6 Timing
The timing of the PCF8534A organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal (SYNC) maintains the correct timing relationship between all the PCF8534As in the system. The timing also generates the LCD frame frequency which is derived as an integer division of the clock frequency (see Table 6). The frame frequency is a fixed division of the internal clock or of the frequency applied to pad CLK when an external clock is used.
Table 6. LCD frame frequencies Nominal frame frequency (Hz) 64
Frame frequency f clk f fr = --------24
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display register, the LCD segment outputs and one column of the display RAM.
7.8 Segment outputs
The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected directly to the LCD. The segment output signals are generated based on the multiplexed backplane signals and with data resident in the display register. When less than 60 segment outputs are required the unused segment outputs must be left open-circuit.
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
16 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
7.9 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane output signals are generated based on the selected LCD drive mode.
* In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required the unused outputs can be left as an open-circuit.
* In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
* In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
* In static drive mode: the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.10 Display RAM
The display RAM is a static 60 x 4-bit RAM which stores LCD data. Logic 1 in the RAM bit map indicates the on-state of the corresponding LCD segment, logic 0 indicates the off-state. There is a direct relationship between RAM addresses and the segment outputs and the individual bits of a RAM word and the backplane outputs. The first RAM row corresponds to the 60 segments operated with respect to backplane BP0 (see Figure 11). In multiplexed LCD applications, the segment data of rows 1 to 4 of the display RAM are time-multiplexed with BP0, BP1, BP2 and BP3, respectively.
display RAM addresses (columns)/segment outputs (S) 0 0 display RAM bits 1 (rows)/ backplane outputs 2 (BP) 3
001aah617
1
2
3
4
55
56
57
58
59
Display RAM bit map showing the direct relationship between backplane outputs, display RAM addresses and segment outputs and between bits in a RAM word and backplane outputs.
Fig 11. Display RAM bit map
When display data is transmitted to the PCF8534A, the display bytes received are stored in the display RAM based on the selected LCD drive mode. Data is stored as it arrives and does not wait for the acknowledge cycle. Depending on the current multiplex mode data is stored singularly, in pairs, triplets or quadruplets. An example of a 7-segment numeric display illustrating the storage order for all drive modes is shown in Figure 12. The RAM storage organization applies equally to other LCD types.
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
17 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
The following applies to Figure 12:
* Static mode: the eight transmitted data bits are placed in row 0 to eight successive
display RAM addresses.
* 1:2 multiplex mode: the eight transmitted data bits are placed in row 0 and 1 to four
successive display RAM addresses.
* 1:3 multiplex mode: the eight transmitted data bits are placed in row 0, 1 and 2 to
three successive addresses. However, bit 2 of the third address is left unchanged. This last bit can, if necessary, be controlled by an additional transfer to this address but avoid overriding adjacent data because full bytes are always transmitted.
* 1:4 multiplex mode: the eight transmitted data bits are placed in row 0, 1, 2 and 3 to
two successive display RAM addresses.
7.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load data pointer command. After this, the data byte is stored starting at the display RAM address indicated by the data pointer (see Figure 12). Once each byte is stored, the data pointer is automatically incremented based on the selected LCD configuration. The contents of the data pointer are incremented as follows:
* * * *
In static drive mode by eight. In 1:2 multiplex drive mode by four. In 1:3 multiplex drive mode by three. In 1:4 multiplex drive mode by two.
If an I2C-bus data access terminates early, the state of the data pointer is unknown. Consequently, the data pointer must be rewritten prior to further RAM accesses.
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
18 of 47
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Product data sheet Rev. 05 -- 6 August 2009
(c) NXP B.V. 2009. All rights reserved. PCF8534A_5
NXP Semiconductors
drive mode
LCD segments
LCD backplanes
display RAM filling order display RAM addresses (columns)/segment outputs (S) byte1
transmitted display byte
Sn+2 Sn+3 static Sn+4 Sn+5 Sn+6
e d f
a b g c
Sn+1 Sn Sn+7 DP
BP0 display RAM bits (rows)/ backplane outputs (BP) 0 1 2 3
n c x x x
n+1 b x x x
n+2 a x x x
n+3 f x x x
n+4 g x x x
n+5 e x x x
n+6 d x x x
n+7 DP x x x MSB cba f LSB g e d DP
BP0 Sn 1:2 Sn+1
f g a b
display RAM addresses (columns)/segment outputs (S) byte1 byte2 n display RAM bits (rows)/ backplane outputs (BP) 0 1 2 3 a b x x n+1 f g x x n+2 e c x x n+3 d DP x x MSB ab f LSB g e c d DP
multiplex Sn+2 Sn+3
e d c
BP1 DP
Sn+1 1:3 Sn+2
f
a b g
BP0 Sn display RAM bits (rows)/ backplane outputs (BP)
display RAM addresses (columns)/segment outputs (S) byte1 byte2 byte3 n 0b 1 DP 2c 3x n+1 a d g x n+2 f e x x MSB b DP c a d g f LSB
multiplex
e d c
Universal LCD driver for low multiplex rates
BP1 DP
BP2
e
display RAM addresses (columns)/segment outputs (S) byte1 byte2 byte3 byte4 byte5 Sn 1:4
f g a b
BP0
BP2 display RAM bits (rows)/ backplane outputs (BP)
n 0a 1c 2b 3 DP
n+1 f e g d MSB a c b DP f LSB egd
multiplex
e c d
BP1 DP
PCF8534A
BP3
Sn+1
001aaj646
x = data bit unchanged.
Fig 12. Relationship between LCD layout, drive mode, display RAM storage order and display data transmitted over the I2C-bus
19 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
7.12 Subaddress counter
The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed only when the contents of the subaddress counter agree with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the device select command (see Table 12). If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is blocked but the data pointer will be incremented as if data storage had taken place. In cascaded applications each PCF8534A in the cascade must be addressed separately. Initially, the first PCF8534A is selected by sending the device select command matching the first device's hardware subaddress. Then the data pointer is set to the preferred display RAM address by sending the load data pointer command. Once the display RAM of the first PCF8534A has been written, the second PCF8534A is selected by sending the device select command again. This time however the command matches the second device's hardware subaddress. Next the load data pointer command is sent to select the preferred display RAM address of the second PCF8534A. This last step is very important because during writing data to the first PCF8534A, the data pointer of the second PCF8534A is incremented. In addition, the hardware subaddress should not be changed whilst the device is being accessed on the I2C-bus interface.
7.13 Output bank selector
The output bank selector (see Table 13), selects one of the four bits per display RAM address for transfer to the display register. The actual bit selected depends on the LCD drive mode in operation and on the instant in the multiplex sequence.
* In 1:4 multiplex mode: all RAM addresses of bit 0 are selected, followed sequentially
by the contents of bit 1, bit 2 and then bit 3.
* In 1:3 multiplex mode: bits 0, 1 and 2 are selected sequentially. * In 1:2 multiplex mode: bits 0 and 1 are selected. * In the static mode: bit 0 is selected.
The SYNC signal resets these sequences to the following starting points: bit 3 for 1:4 multiplex, bit 2 for 1:3 multiplex, bit 1 for 1:2 multiplex and bit 0 for static mode. The PCF8534A includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In static drive mode, the bank select command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 multiplex drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This enables preparation of display information in an alternative bank and the ability to switch to it once it has been assembled.
7.14 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in bit 2 in static drive mode or in bits 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. The input bank selector functions independently to the output bank selector.
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
20 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
7.15 Blinker
The display blinking capabilities of the PCF8534A are very versatile. The whole display can be blinked at frequencies set by the blink select command (see Table 14). The blinking frequencies are fractions of the clock frequency. The ratios between the clock and blinking frequencies depend on the mode in which the device is operating (see Table 7).
Table 7. Blink frequencies Assuming that fclk = 1536 Hz. Blink mode Off 1 Operating mode ratio f clk f blink = --------768 f clk f blink = ----------1536 f clk f blink = ----------3072 Blink frequency Blinking off 2 Hz
2
1 Hz
3
0.5 Hz
An additional feature is for the arbitrary selection of LCD segments to be blinked. This applies to the static and 1:2 multiplex drive modes and is implemented without any communication overheads. Using the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blinking frequency. This mode can also be specified by the blink select command. In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. If the entire display needs to be blinked at a frequency other than the nominal blinking frequency, this can be done using the mode set command to set and reset the display enable bit E at the required rate (see Table 10).
8. Basic architecture
8.1 Characteristics of the I2C-bus
The I2C-bus provides bidirectional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When connected to the output stages of a device, both lines must be connected to a positive supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.
8.1.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Figure 13.
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
21 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 13. Bit transfer
8.1.1.1
START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP condition (P). The START and STOP conditions are illustrated in Figure 14.
SDA
SDA
SCL S START condition P STOP condition
SCL
mbc622
Fig 14. Definition of START and STOP conditions
8.1.2 System configuration
A device generating a message is a `transmitter' and a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'. The system configuration is illustrated in Figure 15.
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
mga807
Fig 15. System configuration
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
22 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
8.1.3 Acknowledge
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle.
* A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
* A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
* The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration).
* A master receiver must signal an end-of-data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the master receiver must leave the data line HIGH during the 9th pulse to not acknowledge. The master will now generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 16.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement
mbc602
1
2
8
9
Fig 16. Acknowledgement of the I2C-bus
8.1.4 PCF8534A I2C-bus controller
The PCF8534A acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8534A are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, the transferred command data and the hardware subaddress. In single device application, the hardware subaddress inputs A0, A1 and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are tied to VSS or VDD using a binary coding scheme so that no two devices with a common I2C-bus slave address have the same hardware subaddress.
8.1.5 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.
PCF8534A_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
23 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
8.2 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8534A. The least significant bit of the slave address is bit R/W. The PCF8534A is a write-only device. It will not respond to a read access, so this bit should always be logic 0. The second bit of the slave address is defined by the level tied at input SA0. Two displays controlled by PCF8534A can be recognized on the same I2C-bus which allows:
* Up to 16 PCF8534As on the same I2C-bus for very large LCD applications * The use of two types of LCD multiplex on the same I2C-bus
The I2C-bus protocol is shown in Figure 18. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the available PCF8534A slave addresses. All PCF8534As with the same SA0 level acknowledge in parallel to the slave address. All PCF8534As with the alternative SA0 level ignore the whole I2C-bus transfer. After acknowledgement, the control byte is sent defining if the next byte is RAM or command information. The control byte also defines if the next byte is a control byte or further RAM/command data (see Figure 17 and Table 8). In this way it is possible to configure the device and then fill the display RAM with little overhead.
MSB 7
6
5
4
3
2
1
LSB 0
CO RS
not relevant
mgl753
Fig 17. Control byte format Table 8. Bit 7 Load data pointer command bit description Symbol CO 0 1 6 RS 0 1 5 to 0 Value Description continue bit last control byte control bytes continue register selection command register data register not relevant
The command bytes and control bytes are also acknowledged by all addressed PCF8534As connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated. The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed PCF8534A. After the last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be issued to RESTART I2C-bus access.
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
24 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
R/W = 0 slave address S CR S011100A0A OS 0 control byte RAM/command byte M AS B L SP B
EXAMPLES a) transmit two bytes of RAM data S S011100A0A01 0 A RAM DATA A RAM DATA AP
b) transmit two command bytes S S011100A0A10 0 A COMMAND A00 A COMMAND AP
c) transmit one command byte and two RAM date bytes S S011100A0A10 0 A COMMAND A01 A RAM DATA A RAM DATA AP
mgl752
Fig 18. I2C-bus protocol
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
25 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
8.3 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. There are five commands:
Table 9. Command Mode set Load data pointer Device select Bank select Blink select Table 10. Bit 7 to 4 3 Definition of commands Opcode 1 0 1 1 1 1 P6 1 1 1 0 P5 1 1 1 0 P4 0 1 1 E P3 0 1 0 B P2 A2 0 A M1 P1 A1 I BF1 M0 P0 A0 O BF0 Reference Table 10 Table 11 Table 12 Table 13 Table 14
Mode set command bit description Symbol E Value 1100 Description fixed value display status the possibility to disable the display allows implementation of blinking under external control 0 1 disabled (blank) enable LCD bias configuration 0 1
1 3 1 2
2
B
bias bias
1 to 0
M[1:0] 01 10 11 00
LCD drive mode selection static; 1 backplane 1:2 multiplex; 2 backplanes 1:3 multiplex; 3 backplanes 1:4 multiplex; 4 backplanes
Table 11. Load data pointer command bit description See Section 7.11. Bit 7 6 to 0 Symbol P[6:0] Value 0 Description fixed value
000 0000 to 7-bit binary value of 0 to 59 011 1011
Table 12. Device select command bit description See Section 7.12. Bit 7 to 3 2 to 0 Symbol A[2:0] Value 1 1100 000 to 111 Description fixed value 3-bit binary value of 0 to 7
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
26 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
Table 13. Bank select command bit description See Section 7.10, Section 7.11, Section 7.12, Section 7.13 and Section 7.14. Bit 7 to 2 1 Symbol I 0 1 0 O 0 1
[1]
Value 11 1110
Description Static fixed value input bank selection: storage of arriving display data RAM bit 0 RAM bit 2 RAM bit 0 RAM bit 2 RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 1:2 multiplex[1]
output bank selection: retrieval of LCD display data
The bank select command has no effect in 1:3 or 1:4 multiplex drive modes.
Table 14. Blink select command bit description See Section 7.15. Bit 7 to 3 2 Symbol A 0 1 1 to 0 BF[1:0] 00 01 10 11
[1]
Value 1 1110
Description fixed value blink mode selection normal blinking[1] blinking by alternating display RAM banks blink frequency selection off 1 2 3
Only normal blinking can be selected in multiplexer 1:3 or 1:4 drive modes.
8.4 Display controller
The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8534A and coordinates their effects. The controller also loads display data into the display RAM as required by the storage order.
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
27 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
9. Internal circuitry
VDD VDD
SA0
VSS VDD
VSS
CLK SCL VSS VDD VSS OSC
VSS VDD SDA
SYNC
VSS VDD
VSS
A0, A1, A2 VLCD VSS VLCD BP0, BP1, BP2, BP3 VSS VLCD VSS
S0 to S59
VSS
001aah615
Fig 19. Device protection diagram
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
28 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
10. Limiting values
CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 15. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IDD VLCD IDD(LCD) ISS VI II VO IO Ptot P/out VESD Ilu Tstg
[1] [2] [3] [4] [5] [6]
Parameter supply voltage supply current LCD supply voltage LCD supply current ground supply current input voltage input current output voltage output current total power dissipation power dissipation per output electrostatic discharge voltage latch-up current storage temperature
Conditions
Min -0.5 -50 -0.5 -50 -50
[1] [1] [1] [2] [1][2]
Max +6.5 +50 +7.5 +50 +50 +6.5 +10 +6.5 +7.5 +10 400 100 3000 200 200 +150
Unit V mA V mA mA V mA V V mA mW mW V V mA C
-0.5 -10 -0.5 -0.5 -10 -
HBM MM
[3] [4] [5] [6]
-65
Pins SDA, SCL, CLK, SYNC, SA0, OSC and A0 to A2. Pins S0 to S59 and BP0 to BP3. HBM: Human Body Model, according to Ref. 6 "JESD22-A114". MM: Machine Model, according to Ref. 7 "JESD22-A115". Latch-up testing, according to Ref. 8 "JESD78". According to the NXP store and transport conditions (see Ref. 10 "SNW-SQ-623") the devices have to be stored at a temperature of +5 C to +45 C and a humidity of 25 % to 75 %.
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
29 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
11. Static characteristics
Table 16. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD VLCD IDD IDD(LCD) Logic VI VIL VIH VPOR IOL IOH IL input voltage LOW-level input voltage HIGH-level input voltage power-on reset voltage LOW-level output current HIGH-level output current leakage current VOL = 0.4 V; VDD = 5 V; on pins CLK and SYNC VOH = 4.6 V; VDD = 5 V; on pin CLK VI = VDD or VSS; on pins SA0, A0 to A2 and CLK VI = VDD; on pin OSC CI VI VIL VIH IOL IL Ci input capacitance input voltage LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance VOL = 0.4 V; VDD = 5 V; on pin SDA VI = VDD or VSS
[2] [2]
Parameter supply voltage LCD supply voltage supply current LCD supply current
Conditions
Min 1.8 2.5
Typ 8 24
Max 5.5 6.5 20 60
Unit V V A A
fclk = 1536 Hz fclk = 1536 Hz
[1] [1]
VSS - 0.5
VDD + 0.5 V 1.3 0.3VDD VDD 1.6 +1 +1 7 5.5 0.3VDD 0.2VDD 5.5 +1 7 V V V mA mA A A pF V V V V mA A pF
on pins CLK, SYNC, OSC, A0 to A2 and SA0 on pins CLK, SYNC, OSC, A0 to A2 and SA0
VSS 0.7VDD 1.0 1 -1 -1 -1 VSS - 0.5
I2C-bus; pins SDA and SCL pin SCL pin SDA VSS VSS 0.7VDD 3 -1 -
LCD outputs Output pins BP0, BP1, BP2 and BP3 VBP RBP VS RS
[1] [2] [3] [4] [5]
voltage on pin BP resistance on pin BP voltage on pin S resistance on pin S
Cbpl = 35 nF VLCD = 5 V Csgm = 35 nF VLCD = 5 V
[3] [4]
-100 -100 -
1.5 6.0
+100 10 +100 13.5
mV k mV k
Output pins S0 to S59
[5] [4]
LCD outputs are open circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. Not tested, design specification only. Cbpl = backplane capacitance. Outputs measured individually and sequentially. Csgm = segment capacitance.
(c) NXP B.V. 2009. All rights reserved.
PCF8534A_5
Product data sheet
Rev. 05 -- 6 August 2009
30 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
12. Dynamic characteristics
Table 17. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Clock Internal: output pin CLK fosc fclk(ext) tclk(H) tclk(L) tPD(SYNC_N) tSYNC_NL tPD(drv) I2C-bus: Pin SCL fSCL tLOW tHIGH Pin SDA tSU;DAT tHD;DAT tBUF tSU;STO tHD;STA tSU;STA tr tf Cb tw(spike)
[1] [2]
Parameter
Conditions
Min
Typ
Max
Unit
oscillator frequency external clock frequency HIGH-level clock time LOW-level clock time SYNC propagation delay SYNC LOW time driver propagation delay timing[2] SCL frequency LOW period of the SCL clock HIGH period of the SCL clock data set-up time data hold time bus free time between a STOP and START condition set-up time for STOP condition hold time (repeated) START condition set-up time for a repeated START condition rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line spike pulse width
VDD = 5 V VDD = 5 V
[1]
960 797 130 130 1
1536 1536 30 -
3046 3046 30
Hz Hz s s ns s s
External: input pin CLK
Synchronization: input pin SYNC
Outputs: pins BP0 to BP3 and S0 to S59 VLCD = 5 V -
1.3 0.6 100 0 1.3 0.6 0.6 0.6 -
-
400 0.3 0.3 400 50
kHz s s ns ns s s s s s s pF ns
Pins SCL and SDA
Typical output (duty cycle = 50 %). All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD.
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
31 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
1 / fclk tclk(H) tclk(L)
0.7VDD CLK
0.3VDD
SYNC
0.7VDD 0.3VDD tPD(SYNC_N) tSYNC_NL 0.5 V
tPD(SYNC_N)
BP0 to BP3, and S0 to S59
tPD(drv)
(VDD = 5 V) 0.5 V
001aah618
Fig 20. Driver timing waveforms
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA tSU;STO
mga728
Fig 21. I2C-bus timing waveforms
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
32 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
13. Application information
13.1 Cascaded operation
Large display configurations of up to 16 PCF8534As can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0).
Table 18. Cluster 1 Addressing cascaded PCF8534A Bit SA0 0 Pin A2 0 0 0 0 1 1 1 1 2 1 0 0 0 0 1 1 1 1 Pin A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Pin A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Device 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
If cascaded PCF8534As are synchronized, they can share the backplane signals from one of the devices in the cascade. This is cost-effective in large LCD applications because the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF8534As in the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Figure 22).
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
33 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
VDD SDA SCL SYNC CLK OSC A0 VLCD VDD tr 2Cb SDA SCL SYNC CLK OSC A1 A2
VLCD
60 segment drives
PCF8534A
BP0 to BP3 (open-circuit) SA0 VSS
LCD PANEL
R
VDD
VLCD
60 segment drives
HOST MICROPROCESSOR/ MICROCONTROLLER
PCF8534A
4 backplanes
BP0 to BP3
VSS
A0
A1
A2
SA0 VSS
001aah619
Fig 22. Cascaded PCF8534A configuration
The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8534As. Synchronization is guaranteed after a power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by defining a multiplex mode when PCF8534As with different SA0 levels are cascaded). SYNC is organized as an input/output pin. The output selection is realized as an open-drain driver with an internal pull-up resistor. A PCF8534A asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is restored by the first PCF8534A to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCF8534A are shown in Figure 23.
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
34 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
Tfr =
1 ffr
BP0
SYNC
(a) static drive mode.
BP0 (1/2 bias)
BP0 (1/3 bias)
SYNC
(b) 1:2 multiplex drive mode.
BP0 (1/3 bias)
SYNC
(c) 1:3 multiplex drive mode.
BP0 (1/3 bias)
SYNC
(d) 1:4 multiplex drive mode.
mgl755
Fig 23. Synchronization of the cascade for various PCF8534A drive modes
The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high, the device will not be able to synchronize properly. Table 19 shows the maximum contact resistance values.
Table 19. 2 3 to 5 6 to 10 11 to 16 SYNC contact resistance Maximum contact resistance 6000 2200 1200 700
Number of devices
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
35 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
14. Package outline
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1
c
y X A 60 61 41 40 Z E
e E HE wM bp pin 1 index 80 1 20 ZD bp D HD wM B vM B vM A 21 detail X Lp L A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.27 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1 Lp 0.75 0.30 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7o o 0
14.15 14.15 13.85 13.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC 136E15 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 24. Package outline SOT315-1 (LQFP80)
PCF8534A_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
36 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
15. Bare die outline
Wire bond die; 76 bonding pads; 2.91 x 2.62 x 0.38 mm PCF8534AU
D e
63 44
A
C1 C2
64
e
PC8534A-1(3)
43
x
76 1
0
E 0 y
24 3
F
4 23
X
0
0.5 scale
1 mm P4 P3
DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A 0.38 D 2.91 E 2.62 0.08 e P1(1) 0.06 P2(2) 0.05 P3(1) 0.10 P4(2) P2 0.09 P1 detail X
Notes 1. Pad size 2. Passivation opening 3. Marking code OUTLINE VERSION PCF8534AU REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 08-08-06
Fig 25. PCF8534AU die outline
PCF8534A_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
37 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
Bonding pad locations Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Coordinates[1] X (m) Y (m) -280 -760.5 -945 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -1238 -841 -761 -681 -601 -521 -441 -361 -281 -201 -121 -41 39 119 301.6 381.6 461.6 541.6
(c) NXP B.V. 2009. All rights reserved.
Table 20. Symbol SDA SCL CLK VDD SYNC OSC A0 A1 A2 SA0 VSS VLCD S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27
PCF8534A_5
Description I2C-bus serial data input and output I2C-bus serial clock input external clock input and output supply voltage cascade synchronization input and output enable input for internal oscillator subaddress counter input
-1384.4 -1384.4 -1384.4 -978.7 -829.3 -714.3 -584.3 -454.3 -324.3 -194.3 -64.3 68.7 173.7 253.7 333.7 413.7 493.7 573.7 653.7 733.7 813.7 893.7 973.7 1384.4 1384.4 1384.4 1384.4 1384.4 1384.4 1384.4 1384.4 1384.4 1384.4 1384.4 1384.4 1384.4 1384.4 1384.4 1384.4 1384.4
I2C-bus slave address input 0 ground input of LCD supply voltage LCD segment output
Product data sheet
Rev. 05 -- 6 August 2009
38 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
Bonding pad locations ...continued Pad 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Coordinates[1] X (m) Y (m) 621.6 701.6 781.6 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 1239.4 935 855 775 695 615 535 375 295 215 125 45 -35 -115 LCD backplane output LCD segment output 1384.4 1384.4 1384.4 896.5 816.5 736.5 576.5 496.5 416.5 336.5 256.5 176.5 96.5 16.5 -63.5 -143.5 -223.5 -303.5 -463.5 -543.5 -623.5 -703.5 -783.5 -1384.4 -1384.4 -1384.4 -1384.4 -1384.4 -1384.4 -1384.4 -1384.4 -1384.4 -1384.4 -1384.4 -1384.4 -1384.4 Description
Table 20. Symbol S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 BP0 BP1 BP2 BP3
[1]
All coordinates are referenced in m to the center of the die (see Figure 25).
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
39 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
REF
REF C1 REF C2
F
001aai649
Fig 26. Alignment marks Table 21. Symbol C1 C2 F
[1]
Alignment mark locations [1] X (m) -1387 1335 -1345 Y (m) 1190 1242 -1173
All coordinates are referenced in m to the center of the die (see Figure 25).
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards.
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
40 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
17. Packing information
A C
1.1
2.1
3.1
x.1 D
1.2
2.2
1.3
F
1.y
B
y E x
001aai625
Fig 27. Tray details for PCF8534AU/DA/1
PC8534A-1
001aai650
Fig 28. Tray alignment for PCF8534AU/DA/1
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
41 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
Tray dimensions Description pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction number of pockets, x direction number of pockets, y direction Value 5.5 mm 4.9 mm 3.08 mm 2.79 mm 50.8 mm 50.8 mm 8 9
Table 22. Symbol A B C D E F N M
18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* Board specifications, including the board finish, solder masks and vias * Package footprints, including solder thieves and orientation * The moisture sensitivity level of the packages
PCF8534A_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
42 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
* Package placement * Inspection and repair * Lead-free soldering versus SnPb soldering 18.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 18.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 29) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 23 and 24
Table 23. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 24. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 29.
PCF8534A_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
43 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 29. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
19. Abbreviations
Table 25. Acronym CMOS ESD HBM IC LCD MM RAM Abbreviations Description Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Human Body Model Integrated Circuit Liquid Crystal Display Machine Model Random Access Memory
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
44 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
20. References
[1] [2] [3] [4] [5] [6] [7] [8] [9] AN10365 -- Surface mount reflow soldering description AN10706 -- Handling bare die IEC 60134 -- Rating systems for electronic tubes and valves and analogous semiconductor devices IEC 61340-5 -- Protection of electronic devices from electrostatic phenomena IPC/JEDEC J-STD-020D -- Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices JESD22-A114 -- Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-A115 -- Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) JESD78 -- IC Latch-Up Test JESD625-A -- Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices
[10] SNW-SQ-623 -- NXP store and transport conditions [11] UM10204 -- I2C-bus specification and user manual
21. Revision history
Table 26. Revision history Release date 20090806 Data sheet status Product data sheet Change notice Supersedes PCF8534A_4 Document ID PCF8534A_5 Modifications:
* * * * * * * * * *
Inserted new drawing for the new product type (Figure 3) Adjusted AEC-Q100 statement Adjusted ESD values (Table 15) Product data sheet PCF8534A_3 Amended new product type Some small changes of the text (to improve style and understanding) Corrected LCD voltage equations Product data sheet Product data sheet PCF8534A_2 PCF8534A_1 Added bare die product and document sections Changes in Section 7.10 on page 14 and Section 7.12 on page 17. Added Caution to Section 10 on page 26. Changed Figure 22 on page 32. Product data sheet -
PCF8534A_4 Modifications:
20090716
PCF8534A_3 Modifications: PCF8534A_2 Modifications:
20081110 20080604
PCF8534A_1
20080423
PCF8534A_5
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
45 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
22. Legal information
22.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Bare die -- All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department.
22.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
23. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCF8534A_5 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 -- 6 August 2009
46 of 47
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
24. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 8 8.1 8.1.1 8.1.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.2 8.3 8.4 9 10 11 12 13 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . 7 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 LCD bias generator. . . . . . . . . . . . . . . . . . . . . . 8 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 8 LCD drive mode waveforms . . . . . . . . . . . . . . 11 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 11 1:2 Multiplex drive mode . . . . . . . . . . . . . . . . . 12 1:3 Multiplex drive mode . . . . . . . . . . . . . . . . . 14 1:4 Multiplex drive mode . . . . . . . . . . . . . . . . . 15 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 16 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Display register . . . . . . . . . . . . . . . . . . . . . . . . 16 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 16 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 17 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Subaddress counter . . . . . . . . . . . . . . . . . . . . 20 Output bank selector. . . . . . . . . . . . . . . . . . . . 20 Input bank selector . . . . . . . . . . . . . . . . . . . . . 20 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Basic architecture . . . . . . . . . . . . . . . . . . . . . . 21 Characteristics of the I2C-bus . . . . . . . . . . . . . 21 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 START and STOP conditions . . . . . . . . . . . . . 22 System configuration . . . . . . . . . . . . . . . . . . . 22 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCF8534A I2C-bus controller . . . . . . . . . . . . . 23 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 24 Command decoder . . . . . . . . . . . . . . . . . . . . . 26 Display controller . . . . . . . . . . . . . . . . . . . . . . 27 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 28 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 29 Static characteristics. . . . . . . . . . . . . . . . . . . . 30 Dynamic characteristics . . . . . . . . . . . . . . . . . 31 Application information. . . . . . . . . . . . . . . . . . 33 13.1 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 21 22 22.1 22.2 22.3 22.4 23 24 Cascaded operation . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 36 37 40 41 42 42 42 43 43 44 45 45 46 46 46 46 46 46 47
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 August 2009 Document identifier: PCF8534A_5

▲Up To Search▲

Price & Availability of PCF8534AHL1

	To Download PCF8534AHL1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .